libsidplayfp  1.8.7
wave.h
1 // ---------------------------------------------------------------------------
2 // This file is part of reSID, a MOS6581 SID emulator engine.
3 // Copyright (C) 2010 Dag Lem <resid@nimrod.no>
4 //
5 // This program is free software; you can redistribute it and/or modify
6 // it under the terms of the GNU General Public License as published by
7 // the Free Software Foundation; either version 2 of the License, or
8 // (at your option) any later version.
9 //
10 // This program is distributed in the hope that it will be useful,
11 // but WITHOUT ANY WARRANTY; without even the implied warranty of
12 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 // GNU General Public License for more details.
14 //
15 // You should have received a copy of the GNU General Public License
16 // along with this program; if not, write to the Free Software
17 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 // ---------------------------------------------------------------------------
19 
20 #ifndef RESID_WAVE_H
21 #define RESID_WAVE_H
22 
23 #include "resid-config.h"
24 
25 namespace reSID
26 {
27 
28 // ----------------------------------------------------------------------------
29 // A 24 bit accumulator is the basis for waveform generation. FREQ is added to
30 // the lower 16 bits of the accumulator each cycle.
31 // The accumulator is set to zero when TEST is set, and starts counting
32 // when TEST is cleared.
33 // The noise waveform is taken from intermediate bits of a 23 bit shift
34 // register. This register is clocked by bit 19 of the accumulator.
35 // ----------------------------------------------------------------------------
37 {
38 public:
40 
41  void set_sync_source(WaveformGenerator*);
42  void set_chip_model(chip_model model);
43 
44  void clock();
45  void clock(cycle_count delta_t);
46  void synchronize();
47  void reset();
48 
49  void writeFREQ_LO(reg8);
50  void writeFREQ_HI(reg8);
51  void writePW_LO(reg8);
52  void writePW_HI(reg8);
53  void writeCONTROL_REG(reg8);
54  reg8 readOSC();
55 
56  // 12-bit waveform output.
57  short output();
58 
59  // Calculate and set waveform output value.
60  void set_waveform_output();
61  void set_waveform_output(cycle_count delta_t);
62 
63 protected:
64  void clock_shift_register();
65  void write_shift_register();
66  void reset_shift_register();
67  void set_noise_output();
68 
69  const WaveformGenerator* sync_source;
70  WaveformGenerator* sync_dest;
71 
72  reg24 accumulator;
73 
74  // Tell whether the accumulator MSB was set high on this cycle.
75  bool msb_rising;
76 
77  // Fout = (Fn*Fclk/16777216)Hz
78  // reg16 freq;
79  reg24 freq;
80  // PWout = (PWn/40.95)%
81  reg12 pw;
82 
83  reg24 shift_register;
84 
85  // Remaining time to fully reset shift register.
86  cycle_count shift_register_reset;
87  // Emulation of pipeline causing bit 19 to clock the shift register.
88  cycle_count shift_pipeline;
89 
90  // Helper variables for waveform table lookup.
91  reg24 ring_msb_mask;
92  unsigned short no_noise;
93  unsigned short noise_output;
94  unsigned short no_noise_or_noise_output;
95  unsigned short no_pulse;
96  unsigned short pulse_output;
97 
98  // The control register right-shifted 4 bits; used for waveform table lookup.
99  reg8 waveform;
100 
101  // The remaining control register bits.
102  reg8 test;
103  reg8 ring_mod;
104  reg8 sync;
105  // The gate bit is handled by the EnvelopeGenerator.
106 
107  // DAC input.
108  reg12 waveform_output;
109  // Fading time for floating DAC input (waveform 0).
110  cycle_count floating_output_ttl;
111 
112  chip_model sid_model;
113 
114  // Sample data for waveforms, not including noise.
115  unsigned short* wave;
116  static unsigned short model_wave[2][8][1 << 12];
117  // DAC lookup tables.
118  static unsigned short model_dac[2][1 << 12];
119 
120 friend class Voice;
121 friend class SID;
122 };
123 
124 
125 // ----------------------------------------------------------------------------
126 // Inline functions.
127 // The following functions are defined inline because they are called every
128 // time a sample is calculated.
129 // ----------------------------------------------------------------------------
130 
131 #if RESID_INLINING || defined(RESID_WAVE_CC)
132 
133 // ----------------------------------------------------------------------------
134 // SID clocking - 1 cycle.
135 // ----------------------------------------------------------------------------
136 RESID_INLINE
137 void WaveformGenerator::clock()
138 {
139  if (unlikely(test)) {
140  // Count down time to fully reset shift register.
141  if (unlikely(shift_register_reset) && unlikely(!--shift_register_reset)) {
142  reset_shift_register();
143  }
144 
145  // The test bit sets pulse high.
146  pulse_output = 0xfff;
147  }
148  else {
149  // Calculate new accumulator value;
150  reg24 accumulator_next = (accumulator + freq) & 0xffffff;
151  reg24 accumulator_bits_set = ~accumulator & accumulator_next;
152  accumulator = accumulator_next;
153 
154  // Check whether the MSB is set high. This is used for synchronization.
155  msb_rising = (accumulator_bits_set & 0x800000) ? true : false;
156 
157  // Shift noise register once for each time accumulator bit 19 is set high.
158  // The shift is delayed 2 cycles.
159  if (unlikely(accumulator_bits_set & 0x080000)) {
160  // Pipeline: Detect rising bit, shift phase 1, shift phase 2.
161  shift_pipeline = 2;
162  }
163  else if (unlikely(shift_pipeline) && !--shift_pipeline) {
164  clock_shift_register();
165  }
166  }
167 }
168 
169 // ----------------------------------------------------------------------------
170 // SID clocking - delta_t cycles.
171 // ----------------------------------------------------------------------------
172 RESID_INLINE
173 void WaveformGenerator::clock(cycle_count delta_t)
174 {
175  if (unlikely(test)) {
176  // Count down time to fully reset shift register.
177  if (shift_register_reset) {
178  shift_register_reset -= delta_t;
179  if (unlikely(shift_register_reset <= 0)) {
180  reset_shift_register();
181  }
182  }
183 
184  // The test bit sets pulse high.
185  pulse_output = 0xfff;
186  }
187  else {
188  // Calculate new accumulator value;
189  reg24 delta_accumulator = delta_t*freq;
190  reg24 accumulator_next = (accumulator + delta_accumulator) & 0xffffff;
191  reg24 accumulator_bits_set = ~accumulator & accumulator_next;
192  accumulator = accumulator_next;
193 
194  // Check whether the MSB is set high. This is used for synchronization.
195  msb_rising = (accumulator_bits_set & 0x800000) ? true : false;
196 
197  // NB! Any pipelined shift register clocking from single cycle clocking
198  // will be lost. It is not worth the trouble to flush the pipeline here.
199 
200  // Shift noise register once for each time accumulator bit 19 is set high.
201  // Bit 19 is set high each time 2^20 (0x100000) is added to the accumulator.
202  reg24 shift_period = 0x100000;
203 
204  while (delta_accumulator) {
205  if (likely(delta_accumulator < shift_period)) {
206  shift_period = delta_accumulator;
207  // Determine whether bit 19 is set on the last period.
208  // NB! Requires two's complement integer.
209  if (likely(shift_period <= 0x080000)) {
210  // Check for flip from 0 to 1.
211  if (((accumulator - shift_period) & 0x080000) || !(accumulator & 0x080000))
212  {
213  break;
214  }
215  }
216  else {
217  // Check for flip from 0 (to 1 or via 1 to 0) or from 1 via 0 to 1.
218  if (((accumulator - shift_period) & 0x080000) && !(accumulator & 0x080000))
219  {
220  break;
221  }
222  }
223  }
224 
225  // Shift the noise/random register.
226  // NB! The two-cycle pipeline delay is only modeled for 1 cycle clocking.
227  clock_shift_register();
228 
229  delta_accumulator -= shift_period;
230  }
231 
232  // Calculate pulse high/low.
233  // NB! The one-cycle pipeline delay is only modeled for 1 cycle clocking.
234  pulse_output = (accumulator >> 12) >= pw ? 0xfff : 0x000;
235  }
236 }
237 
238 
239 // ----------------------------------------------------------------------------
240 // Synchronize oscillators.
241 // This must be done after all the oscillators have been clock()'ed since the
242 // oscillators operate in parallel.
243 // Note that the oscillators must be clocked exactly on the cycle when the
244 // MSB is set high for hard sync to operate correctly. See SID::clock().
245 // ----------------------------------------------------------------------------
246 RESID_INLINE
247 void WaveformGenerator::synchronize()
248 {
249  // A special case occurs when a sync source is synced itself on the same
250  // cycle as when its MSB is set high. In this case the destination will
251  // not be synced. This has been verified by sampling OSC3.
252  if (unlikely(msb_rising) && sync_dest->sync && !(sync && sync_source->msb_rising)) {
253  sync_dest->accumulator = 0;
254  }
255 }
256 
257 
258 // ----------------------------------------------------------------------------
259 // Waveform output.
260 // The output from SID 8580 is delayed one cycle compared to SID 6581;
261 // this is only modeled for single cycle clocking (see sid.cc).
262 // ----------------------------------------------------------------------------
263 
264 // No waveform:
265 // When no waveform is selected, the DAC input is floating.
266 //
267 
268 // Triangle:
269 // The upper 12 bits of the accumulator are used.
270 // The MSB is used to create the falling edge of the triangle by inverting
271 // the lower 11 bits. The MSB is thrown away and the lower 11 bits are
272 // left-shifted (half the resolution, full amplitude).
273 // Ring modulation substitutes the MSB with MSB EOR sync_source MSB.
274 //
275 
276 // Sawtooth:
277 // The output is identical to the upper 12 bits of the accumulator.
278 //
279 
280 // Pulse:
281 // The upper 12 bits of the accumulator are used.
282 // These bits are compared to the pulse width register by a 12 bit digital
283 // comparator; output is either all one or all zero bits.
284 // The pulse setting is delayed one cycle after the compare; this is only
285 // modeled for single cycle clocking.
286 //
287 // The test bit, when set to one, holds the pulse waveform output at 0xfff
288 // regardless of the pulse width setting.
289 //
290 
291 // Noise:
292 // The noise output is taken from intermediate bits of a 23-bit shift register
293 // which is clocked by bit 19 of the accumulator.
294 // The shift is delayed 2 cycles after bit 19 is set high; this is only
295 // modeled for single cycle clocking.
296 //
297 // Operation: Calculate EOR result, shift register, set bit 0 = result.
298 //
299 // reset -------------------------------------------
300 // | | |
301 // test--OR-->EOR<-- |
302 // | | |
303 // 2 2 2 1 1 1 1 1 1 1 1 1 1 |
304 // Register bits: 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 <---
305 // | | | | | | | |
306 // Waveform bits: 1 1 9 8 7 6 5 4
307 // 1 0
308 //
309 // The low 4 waveform bits are zero (grounded).
310 //
311 
312 RESID_INLINE void WaveformGenerator::clock_shift_register()
313 {
314  // bit0 = (bit22 | test) ^ bit17
315  reg24 bit0 = ((shift_register >> 22) ^ (shift_register >> 17)) & 0x1;
316  shift_register = ((shift_register << 1) | bit0) & 0x7fffff;
317 
318  // New noise waveform output.
319  set_noise_output();
320 }
321 
322 RESID_INLINE void WaveformGenerator::write_shift_register()
323 {
324  // Write changes to the shift register output caused by combined waveforms
325  // back into the shift register.
326  // A bit once set to zero cannot be changed, hence the and'ing.
327  // FIXME: Write test program to check the effect of 1 bits and whether
328  // neighboring bits are affected.
329 
330  shift_register &=
331  ~((1<<20)|(1<<18)|(1<<14)|(1<<11)|(1<<9)|(1<<5)|(1<<2)|(1<<0)) |
332  ((waveform_output & 0x800) << 9) | // Bit 11 -> bit 20
333  ((waveform_output & 0x400) << 8) | // Bit 10 -> bit 18
334  ((waveform_output & 0x200) << 5) | // Bit 9 -> bit 14
335  ((waveform_output & 0x100) << 3) | // Bit 8 -> bit 11
336  ((waveform_output & 0x080) << 2) | // Bit 7 -> bit 9
337  ((waveform_output & 0x040) >> 1) | // Bit 6 -> bit 5
338  ((waveform_output & 0x020) >> 3) | // Bit 5 -> bit 2
339  ((waveform_output & 0x010) >> 4); // Bit 4 -> bit 0
340 
341  noise_output &= waveform_output;
342  no_noise_or_noise_output = no_noise | noise_output;
343 }
344 
345 RESID_INLINE void WaveformGenerator::reset_shift_register()
346 {
347  shift_register = 0x7fffff;
348  shift_register_reset = 0;
349 
350  // New noise waveform output.
351  set_noise_output();
352 }
353 
354 RESID_INLINE void WaveformGenerator::set_noise_output()
355 {
356  noise_output =
357  ((shift_register & 0x100000) >> 9) |
358  ((shift_register & 0x040000) >> 8) |
359  ((shift_register & 0x004000) >> 5) |
360  ((shift_register & 0x000800) >> 3) |
361  ((shift_register & 0x000200) >> 2) |
362  ((shift_register & 0x000020) << 1) |
363  ((shift_register & 0x000004) << 3) |
364  ((shift_register & 0x000001) << 4);
365 
366  no_noise_or_noise_output = no_noise | noise_output;
367 }
368 
369 // Combined waveforms:
370 // By combining waveforms, the bits of each waveform are effectively short
371 // circuited. A zero bit in one waveform will result in a zero output bit
372 // (thus the infamous claim that the waveforms are AND'ed).
373 // However, a zero bit in one waveform may also affect the neighboring bits
374 // in the output.
375 //
376 // Example:
377 //
378 // 1 1
379 // Bit # 1 0 9 8 7 6 5 4 3 2 1 0
380 // -----------------------
381 // Sawtooth 0 0 0 1 1 1 1 1 1 0 0 0
382 //
383 // Triangle 0 0 1 1 1 1 1 1 0 0 0 0
384 //
385 // AND 0 0 0 1 1 1 1 1 0 0 0 0
386 //
387 // Output 0 0 0 0 1 1 1 0 0 0 0 0
388 //
389 //
390 // Re-vectorized die photographs reveal the mechanism behind this behavior.
391 // Each waveform selector bit acts as a switch, which directly connects
392 // internal outputs into the waveform DAC inputs as follows:
393 //
394 // * Noise outputs the shift register bits to DAC inputs as described above.
395 // Each output is also used as input to the next bit when the shift register
396 // is shifted.
397 // * Pulse connects a single line to all DAC inputs. The line is connected to
398 // either 5V (pulse on) or 0V (pulse off) at bit 11, and ends at bit 0.
399 // * Triangle connects the upper 11 bits of the (MSB EOR'ed) accumulator to the
400 // DAC inputs, so that DAC bit 0 = 0, DAC bit n = accumulator bit n - 1.
401 // * Sawtooth connects the upper 12 bits of the accumulator to the DAC inputs,
402 // so that DAC bit n = accumulator bit n. Sawtooth blocks out the MSB from
403 // the EOR used to generate the triangle waveform.
404 //
405 // We can thus draw the following conclusions:
406 //
407 // * The shift register may be written to by combined waveforms.
408 // * The pulse waveform interconnects all bits in combined waveforms via the
409 // pulse line.
410 // * The combination of triangle and sawtooth interconnects neighboring bits
411 // of the sawtooth waveform.
412 //
413 // This behavior would be quite difficult to model exactly, since the short
414 // circuits are not binary, but are subject to analog effects. Tests show that
415 // minor (1 bit) differences can actually occur in the output from otherwise
416 // identical samples from OSC3 when waveforms are combined. To further
417 // complicate the situation the output changes slightly with time (more
418 // neighboring bits are successively set) when the 12-bit waveform
419 // registers are kept unchanged.
420 //
421 // The output is instead approximated by using the upper bits of the
422 // accumulator as an index to look up the combined output in a table
423 // containing actual combined waveform samples from OSC3.
424 // These samples are 8 bit, so 4 bits of waveform resolution is lost.
425 // All OSC3 samples are taken with FREQ=0x1000, adding a 1 to the upper 12
426 // bits of the accumulator each cycle for a sample period of 4096 cycles.
427 //
428 // Sawtooth+Triangle:
429 // The accumulator is used to look up an OSC3 sample.
430 //
431 // Pulse+Triangle:
432 // The accumulator is used to look up an OSC3 sample. When ring modulation is
433 // selected, the accumulator MSB is substituted with MSB EOR sync_source MSB.
434 //
435 // Pulse+Sawtooth:
436 // The accumulator is used to look up an OSC3 sample.
437 // The sample is output if the pulse output is on.
438 //
439 // Pulse+Sawtooth+Triangle:
440 // The accumulator is used to look up an OSC3 sample.
441 // The sample is output if the pulse output is on.
442 //
443 // Combined waveforms including noise:
444 // All waveform combinations including noise output zero after a few cycles,
445 // since the waveform bits are and'ed into the shift register via the shift
446 // register outputs.
447 
448 RESID_INLINE
449 void WaveformGenerator::set_waveform_output()
450 {
451  // Set output value.
452  if (likely(waveform)) {
453  // The bit masks no_pulse and no_noise are used to achieve branch-free
454  // calculation of the output value.
455  int ix = (accumulator ^ (sync_source->accumulator & ring_msb_mask)) >> 12;
456  waveform_output =
457  wave[ix] & (no_pulse | pulse_output) & no_noise_or_noise_output;
458  if (unlikely(waveform > 0x8)) {
459  // Combined waveforms write to the shift register.
460  write_shift_register();
461  }
462  }
463  else {
464  // Age floating DAC input.
465  if (likely(floating_output_ttl) && unlikely(!--floating_output_ttl)) {
466  waveform_output = 0;
467  }
468  }
469 
470  // The pulse level is defined as (accumulator >> 12) >= pw ? 0xfff : 0x000.
471  // The expression -((accumulator >> 12) >= pw) & 0xfff yields the same
472  // results without any branching (and thus without any pipeline stalls).
473  // NB! This expression relies on that the result of a boolean expression
474  // is either 0 or 1, and furthermore requires two's complement integer.
475  // A few more cycles may be saved by storing the pulse width left shifted
476  // 12 bits, and dropping the and with 0xfff (this is valid since pulse is
477  // used as a bit mask on 12 bit values), yielding the expression
478  // -(accumulator >= pw24). However this only results in negligible savings.
479 
480  // The result of the pulse width compare is delayed one cycle.
481  // Push next pulse level into pulse level pipeline.
482  pulse_output = -((accumulator >> 12) >= pw) & 0xfff;
483 }
484 
485 RESID_INLINE
486 void WaveformGenerator::set_waveform_output(cycle_count delta_t)
487 {
488  // Set output value.
489  if (likely(waveform)) {
490  // The bit masks no_pulse and no_noise are used to achieve branch-free
491  // calculation of the output value.
492  int ix = (accumulator ^ (sync_source->accumulator & ring_msb_mask)) >> 12;
493  waveform_output =
494  wave[ix] & (no_pulse | pulse_output) & no_noise_or_noise_output;
495  if (unlikely(waveform > 0x8)) {
496  // Combined waveforms write to the shift register.
497  // NB! Since cycles are skipped in delta_t clocking, writes will be
498  // missed. Single cycle clocking must be used for 100% correct operation.
499  write_shift_register();
500  }
501  }
502  else {
503  if (likely(floating_output_ttl)) {
504  // Age floating D/A output.
505  floating_output_ttl -= delta_t;
506  if (unlikely(floating_output_ttl <= 0)) {
507  floating_output_ttl = 0;
508  waveform_output = 0;
509  }
510  }
511  }
512 }
513 
514 
515 // ----------------------------------------------------------------------------
516 // Waveform output (12 bits).
517 // ----------------------------------------------------------------------------
518 
519 // The digital waveform output is converted to an analog signal by a 12-bit
520 // DAC. Re-vectorized die photographs reveal that the DAC is an R-2R ladder
521 // built up as follows:
522 //
523 // 12V 11 10 9 8 7 6 5 4 3 2 1 0 GND
524 // Strange | | | | | | | | | | | | | | Missing
525 // part 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R term.
526 // (bias) | | | | | | | | | | | | | |
527 // --R- --R---R---R---R---R---R---R---R---R---R---R-- ---
528 // | _____
529 // __|__ __|__ |
530 // ----- ===== |
531 // | | | | |
532 // 12V --- ----- ------- GND
533 // |
534 // wout
535 //
536 // Bit on: 5V
537 // Bit off: 0V (GND)
538 //
539 // As is the case with all MOS 6581 DACs, the termination to (virtual) ground
540 // at bit 0 is missing. The MOS 8580 has correct termination, and has also
541 // done away with the bias part on the left hand side of the figure above.
542 //
543 
544 RESID_INLINE
545 short WaveformGenerator::output()
546 {
547  // DAC imperfections are emulated by using waveform_output as an index
548  // into a DAC lookup table. readOSC() uses waveform_output directly.
549  return model_dac[sid_model][waveform_output];
550 }
551 
552 #endif // RESID_INLINING || defined(RESID_WAVE_CC)
553 
554 } // namespace reSID
555 
556 #endif // not RESID_WAVE_H
Definition: dac.cc:45
Definition: wave.h:36
Definition: sid.h:34
Definition: voice.h:30