25 #include "resid-config.h" 40 void set_chip_model(chip_model model);
41 void set_voice_mask(reg4 mask);
42 void enable_filter(
bool enable);
43 void adjust_filter_bias(
double dac_bias);
44 void enable_external_filter(
bool enable);
45 bool set_sampling_parameters(
double clock_freq, sampling_method method,
46 double sample_freq,
double pass_freq = -1,
47 double filter_scale = 0.97);
48 void adjust_sampling_frequency(
double sample_freq);
51 void clock(cycle_count delta_t);
52 int clock(cycle_count& delta_t,
short* buf,
int n,
int interleave = 1);
56 reg8 read(reg8 offset);
57 void write(reg8 offset, reg8 value);
65 char sid_register[0x20];
68 cycle_count bus_value_ttl;
69 cycle_count write_pipeline;
74 reg24 shift_register[3];
75 cycle_count shift_register_reset[3];
76 cycle_count shift_pipeline[3];
77 reg16 pulse_output[3];
78 cycle_count floating_output_ttl[3];
80 reg16 rate_counter[3];
81 reg16 rate_counter_period[3];
82 reg16 exponential_counter[3];
83 reg16 exponential_counter_period[3];
84 reg8 envelope_counter[3];
85 EnvelopeGenerator::State envelope_state[3];
87 cycle_count envelope_pipeline[3];
91 void write_state(
const State& state);
94 void input(
short sample);
100 static double I0(
double x);
101 int clock_fast(cycle_count& delta_t,
short* buf,
int n,
int interleave);
102 int clock_interpolate(cycle_count& delta_t,
short* buf,
int n,
104 int clock_resample(cycle_count& delta_t,
short* buf,
int n,
int interleave);
105 int clock_resample_fastmem(cycle_count& delta_t,
short* buf,
int n,
109 chip_model sid_model;
117 cycle_count bus_value_ttl;
120 cycle_count write_pipeline;
123 double clock_frequency;
135 FIR_RES_FASTMEM = 51473,
139 RINGMASK = RINGSIZE - 1,
147 sampling_method sampling;
148 cycle_count cycles_per_sample;
149 cycle_count sample_offset;
151 short sample_prev, sample_now;
155 double fir_f_cycles_per_sample;
156 double fir_filter_scale;
172 #if RESID_INLINING || defined(RESID_SID_CC) 180 return extfilt.output();
193 for (i = 0; i < 3; i++) {
194 voice[i].envelope.clock();
198 for (i = 0; i < 3; i++) {
199 voice[i].wave.clock();
203 for (i = 0; i < 3; i++) {
204 voice[i].wave.synchronize();
208 for (i = 0; i < 3; i++) {
209 voice[i].wave.set_waveform_output();
213 filter.clock(voice[0].output(), voice[1].output(), voice[2].output());
216 extfilt.clock(filter.output());
219 if (unlikely(write_pipeline)) {
224 if (unlikely(!--bus_value_ttl)) {
229 #endif // RESID_INLINING || defined(RESID_SID_CC) 233 #endif // not RESID_SID_H