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00026 #ifndef _USRP_REV1_REGS_H_
00027 #define _USRP_REV1_REGS_H_
00028
00029 #include "fx2regs.h"
00030
00031
00032
00033
00034
00035 #define USRP_PA IOA // Port A
00036 #define USRP_PA_OE OEA // Port A direction register
00037
00038 #define bmPA_S_CLK bmBIT0 // SPI serial clock
00039 #define bmPA_S_DATA_TO_PERIPH bmBIT1 // SPI SDI (peripheral rel name)
00040 #define bmPA_S_DATA_FROM_PERIPH bmBIT2 // SPI SDO (peripheral rel name)
00041 #define bmPA_SEN_FPGA bmBIT3 // serial enable for FPGA (active low)
00042 #define bmPA_SEN_CODEC_A bmBIT4 // serial enable AD9862 A (active low)
00043 #define bmPA_SEN_CODEC_B bmBIT5 // serial enable AD9862 B (active low)
00044
00045
00046 #define bmPA_RX_OVERRUN bmBIT6 // misc pin to FPGA (overflow)
00047 #define bmPA_TX_UNDERRUN bmBIT7 // misc pin to FPGA (underflow)
00048
00049
00050 sbit at 0x80+0 bitS_CLK;
00051 sbit at 0x80+1 bitS_OUT;
00052 sbit at 0x80+2 bitS_IN;
00053
00054
00055
00056
00057 #define bmPORT_A_OUTPUTS (bmPA_S_CLK \
00058 | bmPA_S_DATA_TO_PERIPH \
00059 | bmPA_SEN_FPGA \
00060 | bmPA_SEN_CODEC_A \
00061 | bmPA_SEN_CODEC_B \
00062 )
00063
00064 #define bmPORT_A_INITIAL (bmPA_SEN_FPGA | bmPA_SEN_CODEC_A | bmPA_SEN_CODEC_B)
00065
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00073
00074 #define USRP_PC IOC // Port C
00075 #define USRP_PC_OE OEC // Port C direction register
00076
00077 #define USRP_ALTERA_CONFIG USRP_PC
00078
00079 #define bmPC_nRESET bmBIT0 // reset line to codecs (active low)
00080 #define bmALTERA_DATA0 bmBIT1
00081 #define bmALTERA_NCONFIG bmBIT2
00082 #define bmALTERA_DCLK bmBIT3
00083 #define bmALTERA_CONF_DONE bmBIT4
00084 #define bmALTERA_NSTATUS bmBIT5
00085 #define bmPC_LED0 bmBIT6 // active low
00086 #define bmPC_LED1 bmBIT7 // active low
00087
00088 sbit at 0xA0+1 bitALTERA_DATA0;
00089 sbit at 0xA0+3 bitALTERA_DCLK;
00090
00091
00092 #define bmALTERA_BITS (bmALTERA_DATA0 \
00093 | bmALTERA_NCONFIG \
00094 | bmALTERA_DCLK \
00095 | bmALTERA_CONF_DONE \
00096 | bmALTERA_NSTATUS)
00097
00098 #define bmPORT_C_OUTPUTS (bmPC_nRESET \
00099 | bmALTERA_DATA0 \
00100 | bmALTERA_NCONFIG \
00101 | bmALTERA_DCLK \
00102 | bmPC_LED0 \
00103 | bmPC_LED1 \
00104 )
00105
00106 #define bmPORT_C_INITIAL (bmPC_LED0 | bmPC_LED1)
00107
00108
00109 #define USRP_LED_REG USRP_PC
00110 #define bmLED0 bmPC_LED0
00111 #define bmLED1 bmPC_LED1
00112
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00116
00117
00118 #define USRP_PE IOE // Port E
00119 #define USRP_PE_OE OEE // Port E direction register
00120
00121 #define bmPE_PE0 bmBIT0 // GPIF debug output
00122 #define bmPE_PE1 bmBIT1 // GPIF debug output
00123 #define bmPE_PE2 bmBIT2 // GPIF debug output
00124 #define bmPE_FPGA_CLR_STATUS bmBIT3 // misc pin to FPGA (clear status)
00125 #define bmPE_SEN_TX_A bmBIT4 // serial enable d'board TX A (active low)
00126 #define bmPE_SEN_RX_A bmBIT5 // serial enable d'board RX A (active low)
00127 #define bmPE_SEN_TX_B bmBIT6 // serial enable d'board TX B (active low)
00128 #define bmPE_SEN_RX_B bmBIT7 // serial enable d'board RX B (active low)
00129
00130
00131 #define bmPORT_E_OUTPUTS (bmPE_FPGA_CLR_STATUS \
00132 | bmPE_SEN_TX_A \
00133 | bmPE_SEN_RX_A \
00134 | bmPE_SEN_TX_B \
00135 | bmPE_SEN_RX_B \
00136 )
00137
00138
00139 #define bmPORT_E_INITIAL (bmPE_SEN_TX_A \
00140 | bmPE_SEN_RX_A \
00141 | bmPE_SEN_TX_B \
00142 | bmPE_SEN_RX_B \
00143 )
00144
00145
00146
00147
00148
00149 #define bmFPGA_HAS_SPACE bmBIT0 // usbrdy[0] has room for 512 byte packet
00150 #define bmFPGA_PKT_AVAIL bmBIT1 // usbrdy[1] has >= 512 bytes available
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00162
00163 #endif