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00020
00021 #ifndef INCLUDED_FPGA_REV1_H
00022 #define INCLUDED_FPGA_REV1_H
00023
00024 void fpga_set_reset (unsigned char v);
00025 void fpga_set_tx_enable (unsigned char v);
00026 void fpga_set_rx_enable (unsigned char v);
00027 void fpga_set_tx_reset (unsigned char v);
00028 void fpga_set_rx_reset (unsigned char v);
00029
00030 unsigned char fpga_has_room_for_packet (void);
00031 unsigned char fpga_has_packet_avail (void);
00032
00033 #if (UC_BOARD_HAS_FPGA)
00034
00035
00036
00037 #define fpga_has_room_for_packet() (GPIFREADYSTAT & bmFPGA_HAS_SPACE)
00038
00039
00040
00041
00042 #define fpga_has_packet_avail() (GPIFREADYSTAT & bmFPGA_PKT_AVAIL)
00043
00044 #else
00045
00046 #define fpga_has_room_for_packet() TRUE
00047 #define fpga_has_packet_avail() TRUE
00048
00049 #endif
00050
00051 #define fpga_clear_flags() \
00052 do { \
00053 USRP_PE |= bmPE_FPGA_CLR_STATUS; \
00054 USRP_PE &= ~bmPE_FPGA_CLR_STATUS; \
00055 } while (0)
00056
00057
00058 #endif