00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021 #ifndef _USRP_COMMANDS_H_
00022 #define _USRP_COMMANDS_H_
00023
00024 #include <usrp_interfaces.h>
00025 #include <usrp_spi_defs.h>
00026
00027 #define MAX_EP0_PKTSIZE 64 // max size of EP0 packet on FX2
00028
00029
00030
00031
00032
00033 #define VRT_VENDOR_IN 0xC0
00034 #define VRT_VENDOR_OUT 0x40
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046 #define VRQ_GET_STATUS 0x80
00047 #define GS_TX_UNDERRUN 0 // wIndexL // returns 1 byte
00048 #define GS_RX_OVERRUN 1 // wIndexL // returns 1 byte
00049
00050 #define VRQ_I2C_READ 0x81 // wValueL: i2c address; length: how much to read
00051
00052 #define VRQ_SPI_READ 0x82 // wValue: optional header bytes
00053
00054
00055
00056
00057
00058
00059 #define VRQ_SET_LED 0x01 // wValueL off/on {0,1}; wIndexL: which {0,1}
00060
00061 #define VRQ_FPGA_LOAD 0x02
00062 # define FL_BEGIN 0 // wIndexL: begin fpga programming cycle. stalls if trouble.
00063 # define FL_XFER 1 // wIndexL: xfer up to 64 bytes of data
00064 # define FL_END 2 // wIndexL: end programming cycle, check for success.
00065
00066
00067 #define VRQ_FPGA_WRITE_REG 0x03 // wIndexL: regno; data: 32-bit regval MSB first
00068 #define VRQ_FPGA_SET_RESET 0x04 // wValueL: {0,1}
00069 #define VRQ_FPGA_SET_TX_ENABLE 0x05 // wValueL: {0,1}
00070 #define VRQ_FPGA_SET_RX_ENABLE 0x06 // wValueL: {0,1}
00071
00072
00073 #define VRQ_SET_SLEEP_BITS 0x07 // wValueH: mask; wValueL: bits. set bits given by mask to bits
00074
00075 # define SLEEP_ADC0 0x01
00076 # define SLEEP_ADC1 0x02
00077 # define SLEEP_DAC0 0x04
00078 # define SLEEP_DAC1 0x08
00079
00080 #define VRQ_I2C_WRITE 0x08 // wValueL: i2c address; data: data
00081
00082 #define VRQ_SPI_WRITE 0x09 // wValue: optional header bytes
00083
00084
00085
00086
00087 #define VRQ_FPGA_SET_TX_RESET 0x0a // wValueL: {0, 1}
00088 #define VRQ_FPGA_SET_RX_RESET 0x0b // wValueL: {0, 1}
00089
00090
00091
00092
00093
00094 #define USRP_HASH_SLOT_0_ADDR 0xe1e0
00095 #define USRP_HASH_SLOT_1_ADDR 0xe1f0
00096
00097
00098
00099 #endif