usrp_basic.h

Go to the documentation of this file.
00001 /* -*- c++ -*- */
00002 /*
00003  * Copyright 2003,2004,2008 Free Software Foundation, Inc.
00004  * 
00005  * This file is part of GNU Radio
00006  * 
00007  * GNU Radio is free software; you can redistribute it and/or modify
00008  * it under the terms of the GNU General Public License as published by
00009  * the Free Software Foundation; either version 3, or (at your option)
00010  * any later version.
00011  * 
00012  * GNU Radio is distributed in the hope that it will be useful,
00013  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00014  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015  * GNU General Public License for more details.
00016  * 
00017  * You should have received a copy of the GNU General Public License
00018  * along with GNU Radio; see the file COPYING.  If not, write to
00019  * the Free Software Foundation, Inc., 51 Franklin Street,
00020  * Boston, MA 02110-1301, USA.
00021  */
00022 
00023 /*
00024  * ----------------------------------------------------------------------
00025  * Mid level interface to the Universal Software Radio Peripheral (Rev 1)
00026  *
00027  * These classes implement the basic functionality for talking to the
00028  * USRP.  They try to be as independent of the signal processing code
00029  * in FPGA as possible.  They implement access to the low level
00030  * peripherals on the board, provide a common way for reading and
00031  * writing registers in the FPGA, and provide the high speed interface
00032  * to streaming data across the USB.
00033  *
00034  * It is expected that subclasses will be derived that provide
00035  * access to the functionality to a particular FPGA configuration.
00036  * ----------------------------------------------------------------------
00037  */
00038 
00039 #ifndef INCLUDED_USRP_BASIC_H
00040 #define INCLUDED_USRP_BASIC_H
00041 
00042 #include <db_base.h>
00043 #include <usrp_slots.h>
00044 #include <string>
00045 #include <vector>
00046 #include <boost/utility.hpp>
00047 #include <usrp_subdev_spec.h>
00048 
00049 struct usb_dev_handle;
00050 class  fusb_devhandle;
00051 class  fusb_ephandle;
00052 
00053 enum txrx_t {
00054   C_RX = 0,
00055   C_TX = 1
00056 };
00057 
00058 /*!
00059  * \brief abstract base class for usrp operations
00060  * \ingroup usrp
00061  */
00062 class usrp_basic : boost::noncopyable
00063 {
00064 protected:
00065   void shutdown_daughterboards();
00066 
00067 protected:
00068   struct usb_dev_handle *d_udh;
00069   int                    d_usb_data_rate;       // bytes/sec
00070   int                    d_bytes_per_poll;      // how often to poll for overruns
00071   bool                   d_verbose;
00072   long                   d_fpga_master_clock_freq;
00073 
00074   static const int       MAX_REGS = 128;
00075   unsigned int           d_fpga_shadows[MAX_REGS];
00076 
00077   int                    d_dbid[2];             // daughterboard ID's (side A, side B)
00078 
00079   /*!
00080    * Shared pointers to subclasses of db_base.
00081    *
00082    * The outer vector is of length 2 (0 = side A, 1 = side B).  The
00083    * inner vectors are of length 1, 2 or 3 depending on the number of
00084    * subdevices implemented by the daugherboard.  At this time, only
00085    * the Basic Rx and LF Rx implement more than 1 subdevice.
00086    */
00087   std::vector< std::vector<db_base_sptr> > d_db;
00088 
00089   //! One time call, made only only from usrp_standard_*::make after shared_ptr is created.
00090   void init_db(usrp_basic_sptr u);
00091 
00092 
00093   usrp_basic (int which_board,
00094               struct usb_dev_handle *open_interface (struct usb_device *dev),
00095               const std::string fpga_filename = "",
00096               const std::string firmware_filename = "");
00097 
00098   /*!
00099    * \brief advise usrp_basic of usb data rate (bytes/sec)
00100    *
00101    * N.B., this doesn't tweak any hardware.  Derived classes
00102    * should call this to inform us of the data rate whenever it's
00103    * first set or if it changes.
00104    *
00105    * \param usb_data_rate       bytes/sec
00106    */
00107   void set_usb_data_rate (int usb_data_rate);
00108   
00109   /*!
00110    * \brief Write auxiliary digital to analog converter.
00111    *
00112    * \param slot        Which Tx or Rx slot to write.
00113    *                    N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
00114    *                    SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
00115    * \param which_dac   [0,3] RX slots must use only 0 and 1.  TX slots must use only 2 and 3.
00116    * \param value       [0,4095]
00117    * \returns true iff successful
00118    */
00119   bool _write_aux_dac (int slot, int which_dac, int value);
00120 
00121   /*!
00122    * \brief Read auxiliary analog to digital converter.
00123    *
00124    * \param slot        2-bit slot number. E.g., SLOT_TX_A
00125    * \param which_adc   [0,1]
00126    * \param value       return 12-bit value [0,4095]
00127    * \returns true iff successful
00128    */
00129   bool _read_aux_adc (int slot, int which_adc, int *value);
00130 
00131   /*!
00132    * \brief Read auxiliary analog to digital converter.
00133    *
00134    * \param slot        2-bit slot number. E.g., SLOT_TX_A
00135    * \param which_adc   [0,1]
00136    * \returns value in the range [0,4095] if successful, else READ_FAILED.
00137    */
00138   int _read_aux_adc (int slot, int which_adc);
00139 
00140 
00141 public:
00142   virtual ~usrp_basic ();
00143 
00144 
00145   /*!
00146    * Return a vector of vectors that contain shared pointers
00147    * to the daughterboard instance(s) associated with the specified side.
00148    *
00149    * It is an error to use the returned objects after the usrp_basic
00150    * object has been destroyed.
00151    */
00152   std::vector<std::vector<db_base_sptr> > db() const { return d_db; }
00153 
00154   /*!
00155    * Return a vector of size >= 1 that contains shared pointers
00156    * to the daughterboard instance(s) associated with the specified side.
00157    *
00158    * \param which_side  [0,1] which daughterboard
00159    *
00160    * It is an error to use the returned objects after the usrp_basic
00161    * object has been destroyed.
00162    */
00163   std::vector<db_base_sptr> db(int which_side);
00164  
00165   /*!
00166    * \brief is the subdev_spec valid?
00167    */
00168   bool is_valid(const usrp_subdev_spec &ss);
00169 
00170   /*!
00171    * \brief given a subdev_spec, return the corresponding daughterboard object.
00172    * \throws std::invalid_ argument if ss is invalid.
00173    *
00174    * \param ss specifies the side and subdevice
00175    */
00176   db_base_sptr selected_subdev(const usrp_subdev_spec &ss);
00177 
00178   /*!
00179    * \brief return frequency of master oscillator on USRP
00180    */
00181   long fpga_master_clock_freq () const { return d_fpga_master_clock_freq; }
00182 
00183   /*!
00184    * Tell API that the master oscillator on the USRP is operating at a non-standard 
00185    * fixed frequency. This is only needed for custom USRP hardware modified to 
00186    * operate at a different frequency from the default factory configuration. This
00187    * function must be called prior to any other API function.
00188    * \param master_clock USRP2 FPGA master clock frequency in Hz (10..64 MHz)
00189    */
00190   void set_fpga_master_clock_freq (long master_clock) { d_fpga_master_clock_freq = master_clock; }
00191 
00192   /*!
00193    * \returns usb data rate in bytes/sec
00194    */
00195   int usb_data_rate () const { return d_usb_data_rate; }
00196 
00197   void set_verbose (bool on) { d_verbose = on; }
00198 
00199   //! magic value used on alternate register read interfaces
00200   static const int READ_FAILED = -99999;
00201 
00202   /*!
00203    * \brief Write EEPROM on motherboard or any daughterboard.
00204    * \param i2c_addr            I2C bus address of EEPROM
00205    * \param eeprom_offset       byte offset in EEPROM to begin writing
00206    * \param buf                 the data to write
00207    * \returns true iff sucessful
00208    */
00209   bool write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf);
00210 
00211   /*!
00212    * \brief Read EEPROM on motherboard or any daughterboard.
00213    * \param i2c_addr            I2C bus address of EEPROM
00214    * \param eeprom_offset       byte offset in EEPROM to begin reading
00215    * \param len                 number of bytes to read
00216    * \returns the data read if successful, else a zero length string.
00217    */
00218   std::string read_eeprom (int i2c_addr, int eeprom_offset, int len);
00219 
00220   /*!
00221    * \brief Write to I2C peripheral
00222    * \param i2c_addr            I2C bus address (7-bits)
00223    * \param buf                 the data to write
00224    * \returns true iff successful
00225    * Writes are limited to a maximum of of 64 bytes.
00226    */
00227   bool write_i2c (int i2c_addr, const std::string buf);
00228 
00229   /*!
00230    * \brief Read from I2C peripheral
00231    * \param i2c_addr            I2C bus address (7-bits)
00232    * \param len                 number of bytes to read
00233    * \returns the data read if successful, else a zero length string.
00234    * Reads are limited to a maximum of 64 bytes.
00235    */
00236   std::string read_i2c (int i2c_addr, int len);
00237 
00238   /*!
00239    * \brief Set ADC offset correction
00240    * \param which_adc   which ADC[0,3]: 0 = RX_A I, 1 = RX_A Q...
00241    * \param offset      16-bit value to subtract from raw ADC input.
00242    */
00243   bool set_adc_offset (int which_adc, int offset);
00244 
00245   /*!
00246    * \brief Set DAC offset correction
00247    * \param which_dac   which DAC[0,3]: 0 = TX_A I, 1 = TX_A Q...
00248    * \param offset      10-bit offset value (ambiguous format:  See AD9862 datasheet).
00249    * \param offset_pin  1-bit value.  If 0 offset applied to -ve differential pin;
00250    *                                  If 1 offset applied to +ve differential pin.
00251    */
00252   bool set_dac_offset (int which_dac, int offset, int offset_pin);
00253 
00254   /*!
00255    * \brief Control ADC input buffer
00256    * \param which_adc   which ADC[0,3]
00257    * \param bypass      if non-zero, bypass input buffer and connect input
00258    *                    directly to switched cap SHA input of RxPGA.
00259    */
00260   bool set_adc_buffer_bypass (int which_adc, bool bypass);
00261 
00262   /*!
00263    * \brief Enable/disable automatic DC offset removal control loop in FPGA
00264    *
00265    * \param bits  which control loops to enable
00266    * \param mask  which \p bits to pay attention to
00267    *
00268    * If the corresponding bit is set, enable the automatic DC
00269    * offset correction control loop.
00270    *
00271    * <pre>
00272    * The 4 low bits are significant:
00273    *
00274    *   ADC0 = (1 << 0)
00275    *   ADC1 = (1 << 1)
00276    *   ADC2 = (1 << 2)
00277    *   ADC3 = (1 << 3)
00278    * </pre>
00279    *
00280    * By default the control loop is enabled on all ADC's.
00281    */
00282   bool set_dc_offset_cl_enable(int bits, int mask);
00283 
00284   /*!
00285    * \brief return the usrp's serial number.
00286    *
00287    * \returns non-zero length string iff successful.
00288    */
00289   std::string serial_number();
00290 
00291   /*!
00292    * \brief Return daughterboard ID for given side [0,1].
00293    *
00294    * \param which_side  [0,1] which daughterboard
00295    *
00296    * \return daughterboard id >= 0 if successful
00297    * \return -1 if no daugherboard
00298    * \return -2 if invalid EEPROM on daughterboard
00299    */
00300   virtual int daughterboard_id (int which_side) const = 0;
00301 
00302   /*!
00303    * \brief Clock ticks to delay rising of T/R signal
00304    * \sa write_atr_mask, write_atr_txval, write_atr_rxval
00305    */
00306   bool write_atr_tx_delay(int value);
00307 
00308   /*!
00309    * \brief Clock ticks to delay falling edge of T/R signal
00310    * \sa write_atr_mask, write_atr_txval, write_atr_rxval
00311    */
00312   bool write_atr_rx_delay(int value);
00313 
00314 
00315   // ================================================================
00316   // Routines to access and control daughterboard specific i/o
00317   //
00318   // Those with a common_ prefix access either the Tx or Rx side depending
00319   // on the txrx parameter.  Those without the common_ prefix are virtual
00320   // and are overriden in usrp_basic_rx and usrp_basic_tx to access the
00321   // the Rx or Tx sides automatically.  We provide the common_ versions
00322   // for those daughterboards such as the WBX and XCVR2450 that share
00323   // h/w resources (such as the LO) between the Tx and Rx sides.
00324 
00325   // ----------------------------------------------------------------
00326   // BEGIN common_  daughterboard control functions
00327 
00328   /*!
00329    * \brief Set Programmable Gain Amplifier(PGA)
00330    *
00331    * \param txrx        Tx or Rx?
00332    * \param which_amp   which amp [0,3]
00333    * \param gain_in_db  gain value(linear in dB)
00334    *
00335    * gain is rounded to closest setting supported by hardware.
00336    *
00337    * \returns true iff sucessful.
00338    *
00339    * \sa pga_min(), pga_max(), pga_db_per_step()
00340    */
00341   bool common_set_pga(txrx_t txrx, int which_amp, double gain_in_db);
00342 
00343   /*!
00344    * \brief Return programmable gain amplifier gain setting in dB.
00345    *
00346    * \param txrx        Tx or Rx?
00347    * \param which_amp   which amp [0,3]
00348    */
00349   double common_pga(txrx_t txrx, int which_amp) const;
00350 
00351   /*!
00352    * \brief Return minimum legal PGA gain in dB.
00353    * \param txrx        Tx or Rx?
00354    */
00355   double common_pga_min(txrx_t txrx) const;
00356 
00357   /*!
00358    * \brief Return maximum legal PGA gain in dB.
00359    * \param txrx        Tx or Rx?
00360    */
00361   double common_pga_max(txrx_t txrx) const;
00362 
00363   /*!
00364    * \brief Return hardware step size of PGA(linear in dB).
00365    * \param txrx        Tx or Rx?
00366    */
00367   double common_pga_db_per_step(txrx_t txrx) const;
00368 
00369   /*!
00370    * \brief Write direction register(output enables) for pins that go to daughterboard.
00371    *
00372    * \param txrx        Tx or Rx?
00373    * \param which_side  [0,1] which size
00374    * \param value       value to write into register
00375    * \param mask        which bits of value to write into reg
00376    *
00377    * Each d'board has 16-bits of general purpose i/o.
00378    * Setting the bit makes it an output from the FPGA to the d'board.
00379    *
00380    * This register is initialized based on a value stored in the
00381    * d'board EEPROM.  In general, you shouldn't be using this routine
00382    * without a very good reason.  Using this method incorrectly will
00383    * kill your USRP motherboard and/or daughterboard.
00384    */
00385   bool _common_write_oe(txrx_t txrx, int which_side, int value, int mask);
00386 
00387   /*!
00388    * \brief Write daughterboard i/o pin value
00389    *
00390    * \param txrx        Tx or Rx?
00391    * \param which_side  [0,1] which d'board
00392    * \param value       value to write into register
00393    * \param mask        which bits of value to write into reg
00394    */
00395   bool common_write_io(txrx_t txrx, int which_side, int value, int mask);
00396 
00397   /*!
00398    * \brief Read daughterboard i/o pin value
00399    *
00400    * \param txrx        Tx or Rx?
00401    * \param which_side  [0,1] which d'board
00402    * \param value       output
00403    */
00404   bool common_read_io(txrx_t txrx, int which_side, int *value);
00405 
00406   /*!
00407    * \brief Read daughterboard i/o pin value
00408    *
00409    * \param txrx        Tx or Rx?
00410    * \param which_side  [0,1] which d'board
00411    * \returns register value if successful, else READ_FAILED
00412    */
00413   int common_read_io(txrx_t txrx, int which_side);
00414 
00415   /*!
00416    * \brief Write daughterboard refclk config register
00417    *
00418    * \param txrx        Tx or Rx?
00419    * \param which_side  [0,1] which d'board
00420    * \param value       value to write into register, see below
00421    *
00422    * <pre>
00423    * Control whether a reference clock is sent to the daughterboards,
00424    * and what frequency.  The refclk is sent on d'board i/o pin 0.
00425    * 
00426    *     3                   2                   1                       
00427    *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
00428    *  +-----------------------------------------------+-+------------+
00429    *  |             Reserved (Must be zero)           |E|   DIVISOR  |
00430    *  +-----------------------------------------------+-+------------+
00431    * 
00432    *  Bit 7  -- 1 turns on refclk, 0 allows IO use
00433    *  Bits 6:0 Divider value
00434    * </pre>
00435    */
00436   bool common_write_refclk(txrx_t txrx, int which_side, int value);
00437 
00438   /*!
00439    * \brief Automatic Transmit/Receive switching
00440    * <pre>
00441    *
00442    * If automatic transmit/receive (ATR) switching is enabled in the
00443    * FR_ATR_CTL register, the presence or absence of data in the FPGA
00444    * transmit fifo selects between two sets of values for each of the 4
00445    * banks of daughterboard i/o pins.
00446    *
00447    * Each daughterboard slot has 3 16-bit registers associated with it:
00448    *   FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
00449    *
00450    * FR_ATR_MASK_{0,1,2,3}: 
00451    *
00452    *   These registers determine which of the daugherboard i/o pins are
00453    *   affected by ATR switching.  If a bit in the mask is set, the
00454    *   corresponding i/o bit is controlled by ATR, else it's output
00455    *   value comes from the normal i/o pin output register:
00456    *   FR_IO_{0,1,2,3}.
00457    *
00458    * FR_ATR_TXVAL_{0,1,2,3}:
00459    * FR_ATR_RXVAL_{0,1,2,3}:
00460    *
00461    *   If the Tx fifo contains data, then the bits from TXVAL that are
00462    *   selected by MASK are output.  Otherwise, the bits from RXVAL that
00463    *   are selected by MASK are output.
00464    * </pre>
00465    */
00466   bool common_write_atr_mask(txrx_t txrx, int which_side, int value);
00467   bool common_write_atr_txval(txrx_t txrx, int which_side, int value);
00468   bool common_write_atr_rxval(txrx_t txrx, int which_side, int value);
00469 
00470   /*!
00471    * \brief Write auxiliary digital to analog converter.
00472    *
00473    * \param txrx        Tx or Rx?
00474    * \param which_side  [0,1] which d'board
00475    *                    N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
00476    *                    SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
00477    * \param which_dac   [2,3] TX slots must use only 2 and 3.
00478    * \param value       [0,4095]
00479    * \returns true iff successful
00480    */
00481   bool common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value);
00482 
00483   /*!
00484    * \brief Read auxiliary analog to digital converter.
00485    *
00486    * \param txrx        Tx or Rx?
00487    * \param which_side  [0,1] which d'board
00488    * \param which_adc   [0,1]
00489    * \param value       return 12-bit value [0,4095]
00490    * \returns true iff successful
00491    */
00492   bool common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value);
00493 
00494   /*!
00495    * \brief Read auxiliary analog to digital converter.
00496    *
00497    * \param txrx        Tx or Rx?
00498    * \param which_side  [0,1] which d'board
00499    * \param which_adc   [0,1]
00500    * \returns value in the range [0,4095] if successful, else READ_FAILED.
00501    */
00502   int common_read_aux_adc(txrx_t txrx, int which_side, int which_adc);
00503 
00504   // END common_ daughterboard control functions
00505   // ----------------------------------------------------------------
00506   // BEGIN virtual daughterboard control functions
00507 
00508   /*!
00509    * \brief Set Programmable Gain Amplifier (PGA)
00510    *
00511    * \param which_amp   which amp [0,3]
00512    * \param gain_in_db  gain value (linear in dB)
00513    *
00514    * gain is rounded to closest setting supported by hardware.
00515    *
00516    * \returns true iff sucessful.
00517    *
00518    * \sa pga_min(), pga_max(), pga_db_per_step()
00519    */
00520   virtual bool set_pga (int which_amp, double gain_in_db) = 0;
00521 
00522   /*!
00523    * \brief Return programmable gain amplifier gain setting in dB.
00524    *
00525    * \param which_amp   which amp [0,3]
00526    */
00527   virtual double pga (int which_amp) const = 0;
00528 
00529   /*!
00530    * \brief Return minimum legal PGA gain in dB.
00531    */
00532   virtual double pga_min () const = 0;
00533 
00534   /*!
00535    * \brief Return maximum legal PGA gain in dB.
00536    */
00537   virtual double pga_max () const = 0;
00538 
00539   /*!
00540    * \brief Return hardware step size of PGA (linear in dB).
00541    */
00542   virtual double pga_db_per_step () const = 0;
00543 
00544   /*!
00545    * \brief Write direction register (output enables) for pins that go to daughterboard.
00546    *
00547    * \param which_side  [0,1] which size
00548    * \param value       value to write into register
00549    * \param mask        which bits of value to write into reg
00550    *
00551    * Each d'board has 16-bits of general purpose i/o.
00552    * Setting the bit makes it an output from the FPGA to the d'board.
00553    *
00554    * This register is initialized based on a value stored in the
00555    * d'board EEPROM.  In general, you shouldn't be using this routine
00556    * without a very good reason.  Using this method incorrectly will
00557    * kill your USRP motherboard and/or daughterboard.
00558    */
00559   virtual bool _write_oe (int which_side, int value, int mask) = 0;
00560 
00561   /*!
00562    * \brief Write daughterboard i/o pin value
00563    *
00564    * \param which_side  [0,1] which d'board
00565    * \param value       value to write into register
00566    * \param mask        which bits of value to write into reg
00567    */
00568   virtual bool write_io (int which_side, int value, int mask) = 0;
00569 
00570   /*!
00571    * \brief Read daughterboard i/o pin value
00572    *
00573    * \param which_side  [0,1] which d'board
00574    * \param value       output
00575    */
00576   virtual bool read_io (int which_side, int *value) = 0;
00577 
00578   /*!
00579    * \brief Read daughterboard i/o pin value
00580    *
00581    * \param which_side  [0,1] which d'board
00582    * \returns register value if successful, else READ_FAILED
00583    */
00584   virtual int read_io (int which_side) = 0;
00585 
00586   /*!
00587    * \brief Write daughterboard refclk config register
00588    *
00589    * \param which_side  [0,1] which d'board
00590    * \param value       value to write into register, see below
00591    *
00592    * <pre>
00593    * Control whether a reference clock is sent to the daughterboards,
00594    * and what frequency.  The refclk is sent on d'board i/o pin 0.
00595    * 
00596    *     3                   2                   1                       
00597    *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
00598    *  +-----------------------------------------------+-+------------+
00599    *  |             Reserved (Must be zero)           |E|   DIVISOR  |
00600    *  +-----------------------------------------------+-+------------+
00601    * 
00602    *  Bit 7  -- 1 turns on refclk, 0 allows IO use
00603    *  Bits 6:0 Divider value
00604    * </pre>
00605    */
00606   virtual bool write_refclk(int which_side, int value) = 0;
00607 
00608   virtual bool write_atr_mask(int which_side, int value) = 0;
00609   virtual bool write_atr_txval(int which_side, int value) = 0;
00610   virtual bool write_atr_rxval(int which_side, int value) = 0;
00611 
00612   /*!
00613    * \brief Write auxiliary digital to analog converter.
00614    *
00615    * \param which_side  [0,1] which d'board
00616    *                    N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
00617    *                    SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
00618    * \param which_dac   [2,3] TX slots must use only 2 and 3.
00619    * \param value       [0,4095]
00620    * \returns true iff successful
00621    */
00622   virtual bool write_aux_dac (int which_side, int which_dac, int value) = 0;
00623 
00624   /*!
00625    * \brief Read auxiliary analog to digital converter.
00626    *
00627    * \param which_side  [0,1] which d'board
00628    * \param which_adc   [0,1]
00629    * \param value       return 12-bit value [0,4095]
00630    * \returns true iff successful
00631    */
00632   virtual bool read_aux_adc (int which_side, int which_adc, int *value) = 0;
00633 
00634   /*!
00635    * \brief Read auxiliary analog to digital converter.
00636    *
00637    * \param which_side  [0,1] which d'board
00638    * \param which_adc   [0,1]
00639    * \returns value in the range [0,4095] if successful, else READ_FAILED.
00640    */
00641   virtual int read_aux_adc (int which_side, int which_adc) = 0;
00642 
00643   /*!
00644    * \brief returns current fusb block size
00645    */
00646   virtual int block_size() const = 0;
00647 
00648   /*!
00649    * \brief returns A/D or D/A converter rate in Hz
00650    */
00651   virtual long converter_rate() const = 0;
00652 
00653   // END virtual daughterboard control functions
00654 
00655   // ----------------------------------------------------------------
00656   // Low level implementation routines.
00657   // You probably shouldn't be using these...
00658   //
00659 
00660   bool _set_led (int which_led, bool on);
00661 
00662   /*!
00663    * \brief Write FPGA register.
00664    * \param regno       7-bit register number
00665    * \param value       32-bit value
00666    * \returns true iff successful
00667    */
00668   bool _write_fpga_reg (int regno, int value);  //< 7-bit regno, 32-bit value
00669 
00670   /*!
00671    * \brief Read FPGA register.
00672    * \param regno       7-bit register number
00673    * \param value       32-bit value
00674    * \returns true iff successful
00675    */
00676   bool _read_fpga_reg (int regno, int *value);  //< 7-bit regno, 32-bit value
00677 
00678   /*!
00679    * \brief Read FPGA register.
00680    * \param regno       7-bit register number
00681    * \returns register value if successful, else READ_FAILED
00682    */
00683   int  _read_fpga_reg (int regno);
00684 
00685   /*!
00686    * \brief Write FPGA register with mask.
00687    * \param regno       7-bit register number
00688    * \param value       16-bit value
00689    * \param mask        16-bit value
00690    * \returns true if successful
00691    * Only use this for registers who actually implement a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
00692    */
00693   bool _write_fpga_reg_masked (int regno, int value, int mask);
00694 
00695   /*!
00696    * \brief Write AD9862 register.
00697    * \param which_codec 0 or 1
00698    * \param regno       6-bit register number
00699    * \param value       8-bit value
00700    * \returns true iff successful
00701    */
00702   bool _write_9862 (int which_codec, int regno, unsigned char value);
00703 
00704   /*!
00705    * \brief Read AD9862 register.
00706    * \param which_codec 0 or 1
00707    * \param regno       6-bit register number
00708    * \param value       8-bit value
00709    * \returns true iff successful
00710    */
00711   bool _read_9862 (int which_codec, int regno, unsigned char *value) const;
00712 
00713   /*!
00714    * \brief Read AD9862 register.
00715    * \param which_codec 0 or 1
00716    * \param regno       6-bit register number
00717    * \returns register value if successful, else READ_FAILED
00718    */
00719   int  _read_9862 (int which_codec, int regno) const;
00720 
00721   /*!
00722    * \brief Write data to SPI bus peripheral.
00723    *
00724    * \param optional_header     0,1 or 2 bytes to write before buf.
00725    * \param enables             bitmask of peripherals to write. See usrp_spi_defs.h
00726    * \param format              transaction format.  See usrp_spi_defs.h SPI_FMT_*
00727    * \param buf                 the data to write
00728    * \returns true iff successful
00729    * Writes are limited to a maximum of 64 bytes.
00730    *
00731    * If \p format specifies that optional_header bytes are present, they are
00732    * written to the peripheral immediately prior to writing \p buf.
00733    */
00734   bool _write_spi (int optional_header, int enables, int format, std::string buf);
00735 
00736   /*
00737    * \brief Read data from SPI bus peripheral.
00738    *
00739    * \param optional_header     0,1 or 2 bytes to write before buf.
00740    * \param enables             bitmask of peripheral to read. See usrp_spi_defs.h
00741    * \param format              transaction format.  See usrp_spi_defs.h SPI_FMT_*
00742    * \param len                 number of bytes to read.  Must be in [0,64].
00743    * \returns the data read if sucessful, else a zero length string.
00744    *
00745    * Reads are limited to a maximum of 64 bytes.
00746    *
00747    * If \p format specifies that optional_header bytes are present, they
00748    * are written to the peripheral first.  Then \p len bytes are read from
00749    * the peripheral and returned.
00750    */
00751   std::string _read_spi (int optional_header, int enables, int format, int len);
00752 
00753   /*!
00754    * \brief Start data transfers.
00755    * Called in base class to derived class order.
00756    */
00757   bool start ();
00758 
00759   /*!
00760    * \brief Stop data transfers.
00761    * Called in base class to derived class order.
00762    */
00763   bool stop ();
00764 };
00765 
00766 /*!
00767  * \brief class for accessing the receive side of the USRP
00768  * \ingroup usrp
00769  */
00770 class usrp_basic_rx : public usrp_basic 
00771 {
00772 private:
00773   fusb_devhandle        *d_devhandle;
00774   fusb_ephandle         *d_ephandle;
00775   int                    d_bytes_seen;          // how many bytes we've seen
00776   bool                   d_first_read;
00777   bool                   d_rx_enable;
00778 
00779 protected:
00780   /*!
00781    * \param which_board      Which USRP board on usb (not particularly useful; use 0)
00782    * \param fusb_block_size  fast usb xfer block size.  Must be a multiple of 512. 
00783    *                         Use zero for a reasonable default.
00784    * \param fusb_nblocks     number of fast usb URBs to allocate.  Use zero for a reasonable default. 
00785    * \param fpga_filename    name of the rbf file to load
00786    * \param firmware_filename name of ihx file to load
00787    */
00788   usrp_basic_rx (int which_board,
00789                  int fusb_block_size=0,
00790                  int fusb_nblocks=0,
00791                  const std::string fpga_filename = "",
00792                  const std::string firmware_filename = ""
00793                  );  // throws if trouble
00794 
00795   bool set_rx_enable (bool on);
00796   bool rx_enable () const { return d_rx_enable; }
00797 
00798   bool disable_rx ();           // conditional disable, return prev state
00799   void restore_rx (bool on);    // conditional set
00800 
00801   void probe_rx_slots (bool verbose);
00802 
00803 public:
00804   ~usrp_basic_rx ();
00805 
00806   /*!
00807    * \brief invokes constructor, returns instance or 0 if trouble
00808    *
00809    * \param which_board      Which USRP board on usb (not particularly useful; use 0)
00810    * \param fusb_block_size  fast usb xfer block size.  Must be a multiple of 512. 
00811    *                         Use zero for a reasonable default.
00812    * \param fusb_nblocks     number of fast usb URBs to allocate.  Use zero for a reasonable default. 
00813    * \param fpga_filename    name of file that contains image to load into FPGA
00814    * \param firmware_filename   name of file that contains image to load into FX2
00815    */
00816   static usrp_basic_rx *make (int which_board,
00817                               int fusb_block_size=0,
00818                               int fusb_nblocks=0,
00819                               const std::string fpga_filename = "",
00820                               const std::string firmware_filename = ""
00821                               );
00822 
00823   /*!
00824    * \brief tell the fpga the rate rx samples are coming from the A/D's
00825    *
00826    * div = fpga_master_clock_freq () / sample_rate
00827    *
00828    * sample_rate is determined by a myriad of registers
00829    * in the 9862.  That's why you have to tell us, so
00830    * we can tell the fpga.
00831    */
00832   bool set_fpga_rx_sample_rate_divisor (unsigned int div);
00833 
00834   /*!
00835    * \brief read data from the D/A's via the FPGA.
00836    * \p len must be a multiple of 512 bytes.
00837    *
00838    * \returns the number of bytes read, or -1 on error.
00839    *
00840    * If overrun is non-NULL it will be set true iff an RX overrun is detected.
00841    */
00842   int read (void *buf, int len, bool *overrun);
00843 
00844 
00845   //! sampling rate of A/D converter
00846   virtual long converter_rate() const { return fpga_master_clock_freq(); } // 64M
00847   long adc_rate() const { return converter_rate(); }
00848   int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
00849 
00850   bool set_pga (int which_amp, double gain_in_db);
00851   double pga (int which_amp) const;
00852   double pga_min () const;
00853   double pga_max () const;
00854   double pga_db_per_step () const;
00855 
00856   bool _write_oe (int which_side, int value, int mask);
00857   bool write_io (int which_side, int value, int mask);
00858   bool read_io (int which_side, int *value);
00859   int read_io (int which_side);
00860   bool write_refclk(int which_side, int value);
00861   bool write_atr_mask(int which_side, int value);
00862   bool write_atr_txval(int which_side, int value);
00863   bool write_atr_rxval(int which_side, int value);
00864 
00865   bool write_aux_dac (int which_side, int which_dac, int value);
00866   bool read_aux_adc (int which_side, int which_adc, int *value);
00867   int  read_aux_adc (int which_side, int which_adc);
00868 
00869   int block_size() const;
00870 
00871   // called in base class to derived class order
00872   bool start ();
00873   bool stop ();
00874 };
00875 
00876 /*!
00877  * \brief class for accessing the transmit side of the USRP
00878  * \ingroup usrp
00879  */
00880 class usrp_basic_tx : public usrp_basic 
00881 {
00882 private:
00883   fusb_devhandle        *d_devhandle;
00884   fusb_ephandle         *d_ephandle;
00885   int                    d_bytes_seen;          // how many bytes we've seen
00886   bool                   d_first_write;
00887   bool                   d_tx_enable;
00888 
00889  protected:
00890   /*!
00891    * \param which_board      Which USRP board on usb (not particularly useful; use 0)
00892    * \param fusb_block_size  fast usb xfer block size.  Must be a multiple of 512.
00893    *                         Use zero for a reasonable default.
00894    * \param fusb_nblocks     number of fast usb URBs to allocate.  Use zero for a reasonable default.
00895    * \param fpga_filename    name of file that contains image to load into FPGA
00896    * \param firmware_filename   name of file that contains image to load into FX2
00897    */
00898   usrp_basic_tx (int which_board,
00899                  int fusb_block_size=0,
00900                  int fusb_nblocks=0,
00901                  const std::string fpga_filename = "",
00902                  const std::string firmware_filename = ""
00903                  );             // throws if trouble
00904 
00905   bool set_tx_enable (bool on);
00906   bool tx_enable () const { return d_tx_enable; }
00907 
00908   bool disable_tx ();           // conditional disable, return prev state
00909   void restore_tx (bool on);    // conditional set
00910 
00911   void probe_tx_slots (bool verbose);
00912 
00913 public:
00914 
00915   ~usrp_basic_tx ();
00916 
00917   /*!
00918    * \brief invokes constructor, returns instance or 0 if trouble
00919    *
00920    * \param which_board      Which USRP board on usb (not particularly useful; use 0)
00921    * \param fusb_block_size  fast usb xfer block size.  Must be a multiple of 512. 
00922    *                         Use zero for a reasonable default.
00923    * \param fusb_nblocks     number of fast usb URBs to allocate.  Use zero for a reasonable default. 
00924    * \param fpga_filename    name of file that contains image to load into FPGA
00925    * \param firmware_filename   name of file that contains image to load into FX2
00926    */
00927   static usrp_basic_tx *make (int which_board, int fusb_block_size=0, int fusb_nblocks=0,
00928                               const std::string fpga_filename = "",
00929                               const std::string firmware_filename = ""
00930                               );
00931 
00932   /*!
00933    * \brief tell the fpga the rate tx samples are going to the D/A's
00934    *
00935    * div = fpga_master_clock_freq () * 2
00936    *
00937    * sample_rate is determined by a myriad of registers
00938    * in the 9862.  That's why you have to tell us, so
00939    * we can tell the fpga.
00940    */
00941   bool set_fpga_tx_sample_rate_divisor (unsigned int div);
00942 
00943   /*!
00944    * \brief Write data to the A/D's via the FPGA.
00945    *
00946    * \p len must be a multiple of 512 bytes.
00947    * \returns number of bytes written or -1 on error.
00948    *
00949    * if \p underrun is non-NULL, it will be set to true iff
00950    * a transmit underrun condition is detected.
00951    */
00952   int write (const void *buf, int len, bool *underrun);
00953 
00954   /*
00955    * Block until all outstanding writes have completed.
00956    * This is typically used to assist with benchmarking
00957    */
00958   void wait_for_completion ();
00959 
00960   //! sampling rate of D/A converter
00961   virtual long converter_rate() const { return fpga_master_clock_freq () * 2; } // 128M
00962   long dac_rate() const { return converter_rate(); }
00963   int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
00964 
00965   bool set_pga (int which_amp, double gain_in_db);
00966   double pga (int which_amp) const;
00967   double pga_min () const;
00968   double pga_max () const;
00969   double pga_db_per_step () const;
00970 
00971   bool _write_oe (int which_side, int value, int mask);
00972   bool write_io (int which_side, int value, int mask);
00973   bool read_io (int which_side, int *value);
00974   int read_io (int which_side);
00975   bool write_refclk(int which_side, int value);
00976   bool write_atr_mask(int which_side, int value);
00977   bool write_atr_txval(int which_side, int value);
00978   bool write_atr_rxval(int which_side, int value);
00979 
00980   bool write_aux_dac (int which_side, int which_dac, int value);
00981   bool read_aux_adc (int which_side, int which_adc, int *value);
00982   int read_aux_adc (int which_side, int which_adc);
00983 
00984   int block_size() const;
00985 
00986   // called in base class to derived class order
00987   bool start ();
00988   bool stop ();
00989 };
00990 
00991 #endif

Generated on Wed Jul 29 07:24:34 2009 for GNU Radio 3.2.2 C++ API by  doxygen 1.5.8