23 #include <rte_config.h> 27 RTE_PGSIZE_4K = 1ULL << 12,
28 RTE_PGSIZE_64K = 1ULL << 16,
29 RTE_PGSIZE_256K = 1ULL << 18,
30 RTE_PGSIZE_2M = 1ULL << 21,
31 RTE_PGSIZE_16M = 1ULL << 24,
32 RTE_PGSIZE_256M = 1ULL << 28,
33 RTE_PGSIZE_512M = 1ULL << 29,
34 RTE_PGSIZE_1G = 1ULL << 30,
35 RTE_PGSIZE_4G = 1ULL << 32,
36 RTE_PGSIZE_16G = 1ULL << 34,
39 #define SOCKET_ID_ANY -1 40 #define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) 42 #define RTE_CACHE_LINE_ROUNDUP(size) \ 43 (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE)) 47 #if RTE_CACHE_LINE_SIZE == 64 48 #define RTE_CACHE_LINE_SIZE_LOG2 6 49 #elif RTE_CACHE_LINE_SIZE == 128 50 #define RTE_CACHE_LINE_SIZE_LOG2 7 52 #error "Unsupported cache line size" 55 #define RTE_CACHE_LINE_MIN_SIZE 64 60 #define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE) 65 #define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE) 68 #define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1) 77 #define RTE_BAD_IOVA ((rte_iova_t)-1)
unsigned rte_memory_get_nchannel(void)
const struct rte_memseg * rte_eal_get_physmem_layout(void)
int rte_eal_using_phys_addrs(void)
int rte_mem_lock_page(const void *virt)
unsigned rte_memory_get_nrank(void)
phys_addr_t rte_mem_virt2phy(const void *virt)
uint64_t rte_eal_get_physmem_size(void)
void rte_dump_physmem_layout(FILE *f)
rte_iova_t rte_mem_virt2iova(const void *virt)