Content-type: text/html
Manpage of VRQ
VRQ
Section: User Commands (1)
Updated: October 2009
Index
Return to Main Contents
NAME
Vrq - manual page for Vrq 1.0.64,
SYNOPSIS
vrq
[
options]
<file1> [
<file2>...]
DESCRIPTION
'Vrq' is a framework for creating verilog based tools.
OPTIONS
- --version
-
Print version
- --help
-
This message
- --bindir
-
Binary install path
- --libdir
-
Library install path
- --pkglibdir
-
Plugin install path
- --includedir
-
Include install path
- --cflags
-
Compiler flags used
- --ldflags
-
Linker flags used
- --libs
-
Libraries used
- -V
-
Verbose
- -y <directory>
-
Search directory for module definitions
- -f <filename>
-
Read options from <filename>
- -v <lib_filename>
-
Search file for module definitions
- -l <filename>
-
Set log file to <filename>
- -w <message>=<policy>
-
Set policy for warning <message> to <policy>; ignore, warning, error, info
- -w all=<policy>
-
Set policy for all warnings to <policy>; ignore, warning, error, info
- -wl
-
List all warning messages
- +libext+<extension>
-
Specify library suffix to <extension>
- -dump
-
Dump internal tree
- -debug
-
Print debug info
- -quiet
-
Print minimal runtime info
- -infervectors
-
Infer reg and wire vectors
- -keeptickdefines
-
Best effort attempt to keep tick defines and `include statements in code (EXPERIMENTAL)
- -macrocheck
-
Do not allow undefined macros
- -o <filename>
-
Specify output file
- -dir <directory>
-
Specify output directory
- -pragma <regexp>
-
Extended regular expression template for pragma comments
- -passthru <name>
-
Pass through ifdef blocks with label
- +incdir+<directory>
-
Specify include search path
- +define+<name>=<value>
-
Define `define
- +<name>+<value>
-
Define plusargs
- -tool builder
-
Auto route hierarchy
- -tool coverage
-
Add line coverage instrumentation
- -tool dump
-
Print verilog output
- -tool flatten
-
Reduce to single level hiearchy
- -tool sim
-
Verilog simulator
- -tool stats
-
Print summary of hiearchy
- -tool xprop
-
Add X propagation instrumentation
* 'builder' Options
- +tree_ext=<ext>
-
File extension for files to be expanded
- +depend=<filename>
-
Generate dependency info
- +builder-verbose
-
Dump vebose log of actions
* 'coverage' Options
-
+coverage_output_file=<filename> Filename for coverage line mapping info
* 'dump' Options
- +dump-fps
-
- Force part selects on all vectors
- +dump-fvl
-
Convert all logical ops to vector ops
- +dump-fcc
-
Convert all comments to c++ style
- +dump-swda
-
Split wire declaration assignments
- +dump-fbae
-
Force begin/end block after event statement
- +dump-nns
-
Replace null statements with begin/end pairs
- +dump-sabo
-
Add spaces around binary operators
- +dump-ced
-
Create explicit declarations for implicitly declared variables
- +dump-strip-attr
-
strip out all attributes
-
+dump-timescale=<timescale> emit `timescale <timescale> statements for all modules missing `timescale declarations
- +dump-simplify
-
- Simplify constant expressions (EXPERIMENTAL)
* 'sim' Options
- +sim-interactive
-
start simulation in interactive mode only
- +sim-compile-only
-
do not simulate, compile only
- +sim-trace
-
enable execution tracing
- +sim-mindelays
-
use minimum delays
- +sim-typdelays
-
use typical delays
- +sim-maxdelays
-
use maximum delays
-
+sim-pli=pliLib1+pliLib2+... load pli librarys
* 'xprop' Options
- +xprop-begin=<pragma>
-
- insertion begin pragma
- +xprop-end=<pragma>
-
insertion end pragma
- +xprop-clk-begin=<pragma>
-
insertion clock begin pragma
- +xprop-clk-end=<pragma>
-
insertion clock end pragma
- +xprop-disable-if
-
disable if instrumentation
- +xprop-disable-case
-
disable case instrumentation
- +xprop-disable-select
-
disable bit/part select instrumentation
- +xprop-disable-array
-
disable array instrumentation
- +xprop-disable-ternary
-
disable '?' instrumentation
- +xprop-nox-attr=<name>
-
attribute specifing variable will never be x
- +xprop-int-nox
-
declare integers will never be x
- +xprop-enable-clock
-
instrument register clocks
-
+xprop-clk-edge-control=[!]<tickdefine> Supply a preprocessor tick define to enable instrumentation on both edges of the clock. ! indicates tickdefine disables both edges. If switch isn't supplied the behavior is single edge unless XPROP_BOTH_EDGES is defined
AUTHOR
Written by Mark Hummel
REPORTING BUGS
Report bugs at <http://sourceforge.net/projects/vrq>
COPYRIGHT
Copyright © 1997-2009 Mark Hummel
Vrq comes with ABSOLUTELY NO WARRANTY; This is free
software, and you are welcome to redistribute it under the
terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License,
or (at your option) any later version.
Index
- NAME
-
- SYNOPSIS
-
- DESCRIPTION
-
- OPTIONS
-
- AUTHOR
-
- REPORTING BUGS
-
- COPYRIGHT
-
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Time: 22:42:23 GMT, October 31, 2009