Instruction-Based Sampling Derived Events

This section describes the derived events for Instruction-Based Sampling (IBS.) IBS is available on AMD Family 10h processors.

IBS fetch derived events

Event Select 0xF000 IBS fetch samples

Abbreviation: IBS fetch

The number of all IBS fetch samples. This derived event counts the number of all IBS fetch samples that were collected including IBS-killed fetch samples.

Event Select 0xF001 IBS fetch killed

Abbreviation: IBS fetch killed

The number of IBS sampled fetches that were killed fetches. A fetch operation is killed if the fetch did not reach ITLB or IC access. The number of killed fetch samples is not generally useful for analysis and are filtered out in other derived IBS fetch events (except Event Select 0xF000 which counts all IBS fetch samples including IBS killed fetch samples.)

Event Select 0xF002 IBS fetch attempted

Abbreviation: IBS fetch attempt

The number of IBS sampled fetches that were not killed fetch attempts. This derived event measures the number of useful fetch attempts and does not include the number of IBS killed fetch samples. This event should be used to compute ratios such as the ratio of IBS fetch IC misses to attempted fetches.

The number of attempted fetches should equal the sum of the number of completed fetches and the number of aborted fetches.

Event Select 0xF003 IBS fetch completed

Abbreviation: IBS fetch comp

The number of IBS sampled fetches that completed. A fetch is completed if the attempted fetch delivers instruction data to the instruction decoder. Although the instruction data was delivered, it may still not be used (e.g., the instruction data may have been on the "wrong path" of an incorrectly predicted branch.)

Event Select 0xF004 IBS fetch aborted

Abbreviation: IBS fetch abort

The number of IBS sampled fetches that aborted. An attempted fetch is aborted if it did not complete and deliver instruction data to the decoder. An attempted fetch may abort at any point in the process of fetching instruction data. An abort may be due to a branch redirection as the result of a mispredicted branch.

The number of IBS aborted fetch samples is a lower bound on the amount of unsuccessful, speculative fetch activity. It is a lower bound since the instruction data delivered by completed fetches may not be used.

Event Select 0xF005 IBS L1 ITLB hit

Abbreviation: IBS L1 ITLB hit

The number of IBS attempted fetch samples where the fetch operation initially hit in the L1 ITLB (Instruction Translation Lookaside Buffer).

Event Select 0xF006 IBS L1 ITLB miss, L2 ITLB hit

Abbreviation: IBS ITLB L1M L2H

The number of IBS attempted fetch samples where the fetch operation initially missed in the L1 ITLB and hit in the L2 ITLB.

Event Select 0xF007 IBS L1 ITLB miss, L2 ITLB miss

Abbreviation: IBS ITLB L1M L2M

The number of IBS attempted fetch samples where the fetch operation initially missed in both the L1 ITLB and the L2 ITLB.

Event Select 0xF008 IBS instruction cache miss

Abbreviation: IBS IC miss

The number of IBS attempted fetch samples where the fetch operation initially missed in the IC (instruction cache).

Event Select 0xF009 IBS instruction cache hit

Abbreviation: IBS IC hit

The number of IBS attempted fetch samples where the fetch operation initially hit in the IC.

Event Select 0xF00A IBS 4-KByte page translation

Abbreviation: IBS 4K page

The number of IBS attempted fetch samples where the fetch operation produced a valid physical address (i.e., address translation completed successfully) and used a 4-KByte page entry in the L1 ITLB.

Event Select 0xF00B IBS 2-MByte page translation

Abbreviation: IBS 2M page

The number of IBS attempted fetch samples where the fetch operation produced a valid physical address (i.e., address translation completed successfully) and used a 2-MByte page entry in the L1 ITLB.

Event Select 0xF00E IBS fetch latency

Abbreviation: IBS fetch lat

The total latency of all IBS attempted fetch samples. Divide the total IBS fetch latency by the number of IBS attempted fetch samples to obtain the average latency of the attempted fetches that were sampled.

IBS op derived events

Event Select 0xF100 IBS all op samples

Abbreviation: IBS all ops

The number of all IBS op samples that were collected. These op samples may be branch ops, resync ops, ops that perform load/store operations, or undifferentiated ops (e.g., those ops that perform arithmetic operations, logical operations, etc.).

IBS collects data for retired ops. No data is collected for ops that are aborted due to pipeline flushes, etc. Thus, all sampled ops are architecturally significant and contribute to the successful forward progress of executing programs.

Event Select 0xF101 IBS tag-to-retire cycles

Abbreviation: IBS tag-to-ret

The total number of tag-to-retire cycles across all IBS op samples. The tag-to-retire time of an op is the number of cycles from when the op was tagged (selected for sampling) to when the op retired.

Event Select 0xF102 IBS completion-to-retire cycles

Abbreviation: IBS comp-to-ret

The total number of completion-to-retire cycles across all IBS op samples. The completion-to-retire time of an op is the number of cycles from when the op completed to when the op retired.

IBS branch/return/resync op derived events

Event Select 0xF103 IBS branch op

Abbreviation: IBS BR

The number of IBS retired branch op samples. A branch operation is a change in program control flow and includes unconditional and conditional branches, subroutine calls and subroutine returns. Branch ops are used to implement AMD64 branch semantics.

Event Select 0xF104 IBS mispredicted branch op

Abbreviation: IBS misp BR

The number of IBS samples for retired branch operations that were mispredicted. This event should be used to compute the ratio of mispredicted branch operations to all branch operations.

Event Select 0xF105 IBS taken branch op

Abbreviation: IBS taken BR

The number of IBS samples for retired branch operations that were taken branches.

Event Select 0xF106 IBS mispredicted taken branch op

Abbreviation: IBS misp taken BR

The number of IBS samples for retired branch operations that were mispredicted taken branches.

Event Select 0xF107 IBS return op

Abbreviation: IBS RET

The number of IBS retired branch op samples where the operation was a subroutine return. These samples are a subset of all IBS retired branch op samples.

Event Select 0xF108 IBS mispredicted return op

Abbreviation: IBS misp RET

The number of IBS retired branch op samples where the operation was a mispredicted subroutine return. This event should be used to compute the ratio of mispredicted returns to all subroutine returns.

Event Select 0xF109 IBS resync op

Abbreviation: IBS resync

The number of IBS resync op samples. A resync op is only found in certain microcoded AMD64 instructions and causes a complete pipeline flush.

IBS load/store derived events

Event Select 0xF200 IBS all load/store ops

Abbreviation: IBS load/store

The number of IBS op samples for ops that perform either a load and/or store operation.

An AMD64 instruction may be translated into one ("single fastpath"), two ("double fastpath"), or several ("vector path") ops. Each op may perform a load operation, a store operation or both a load and store operation (each to the same address). Some op samples attributed to an AMD64 instruction may perform a load/store operation while other op samples attributed to the same instruction may not. Further, some branch instructions perform load/store operations. Thus, a mix of op sample types may be attributed to a single AMD64 instruction depending upon the ops that are issued from the AMD64 instruction and the op types.

Event Select 0xF201 IBS load ops

Abbreviation: IBS load

The number of IBS op samples for ops that perform a load operation.

Event Select 0xF202 IBS store ops

Abbreviation: IBS store

The number of IBS op samples for ops that perform a store operation.

Event Select 0xF203 IBS L1 DTLB hit

Abbreviation: IBS L1 DTLB hit

The number of IBS op samples where either a load or store operation initially hit in the L1 DTLB (data translation lookaside buffer).

Event Select 0xF204 IBS L1 DTLB miss, L2 DTLB hit

Abbreviation: IBS DTLB L1M L2H

The number of IBS op samples where either a load or store operation initially missed in the L1 DTLB and hit in the L2 DTLB.

Event Select 0xF205 IBS L1 DTLB miss, L2 DTLM miss

Abbreviation: IBS DTLB L1M L2M

The number of IBS op samples where either a load or store operation initially missed in both the L1 DTLB and the L2 DTLB.

Event Select 0xF206 IBS DC miss

Abbreviation: IBS DC miss

The number of IBS op samples where either a load or store operation initially missed in the data cache (DC).

Event Select 0xF207 IBS DC hit

Abbreviation: IBS DC hit

The number of IBS op samples where either a load or store operation initially hit in the data cache (DC).

Event Select 0xF208 IBS misaligned access

Abbreviation: IBS misalign acc

The number of IBS op samples where either a load or store operation caused a misaligned access (i.e., the load or store operation crossed a 128-bit boundary).

Event Select 0xF209 IBS bank conflict on load op

Abbreviation: IBS bank conf load

The number of IBS op samples where either a load or store operation caused a bank conflict with a load operation.

Event Select 0xF20A IBS bank conflict on store op

Abbreviation: IBS bank conf store

The number of IBS op samples where either a load or store operation caused a bank conflict with a store operation.

Event Select 0xF20B IBS store-to-load forwarded

Abbreviation: IBS forwarded

The number of IBS op samples where data for a load operation was forwarded from a store operation.

Event Select 0xF20C IBS store-to-load cancelled

Abbreviation: IBS cancelled

The number of IBS op samples where data forwarding to a load operation from a store was cancelled.

Event Select 0xF20D IBS UC memory access

Abbreviation: IBS UC mem acc

The number of IBS op samples where a load or store operation accessed uncacheable (UC) memory.

Event Select 0xF20E IBS WC memory access

Abbreviation: IBS WC mem acc

The number of IBS op samples where a load or store operation accessed write combining (WC) memory.

Event Select 0xF20F IBS locked operation

Abbreviation: IBS locked op

The number of IBS op samples where a load or store operation was a locked operation.

Event Select 0xF210 IBS MAB hit

Abbreviation: IBS MAB hit

The number of IBS op samples where a load or store operation hit an already allocated entry in the Miss Address Buffer (MAB).

Event Select 0xF211 IBS L1 DTLB 4-KByte page

Abbreviation: IBS L1 DTLB 4K

The number of IBS op samples where a load or store operation produced a valid linear (virtual) address and a 4-KByte page entry in the L1 DTLB was used for address translation.

Event Select 0xF212 IBS L1 DTLB 2-MByte page

Abbreviation: IBS L1 DTLB 2M

The number of IBS op samples where a load or store operation produced a valid linear (virtual) address and a 2-MByte page entry in the L1 DTLB was used for address translation.

Event Select 0xF213 IBS L1 DTLB 1-GByte page

Abbreviation: IBS L1 DTLB 1G

The number of IBS op samples where a load or store operation produced a valid linear (virtual) address and a 1-GByte page entry in the L1 DTLB was used for address translation.

Event Select 0xF215 IBS L2 DTLB 4K page

Abbreviation: IBS L2 DTLB 4K

The number of IBS op samples where a load or store operation produced a valid linear (virtual) address, hit the L2 DTLB, and used a 4 KByte page entry for address translation.

Event Select 0xF216 IBS L2 DTLB 2-MByte page

Abbreviation: IBS L2 DTLB 2M

The number of IBS op samples where a load or store operation produced a valid linear (virtual) address, hit the L2 DTLB, and used a 2-MByte page entry for address translation.

Event Select 0xF219 IBS DC miss load latency

Abbreviation: IBS DC load lat

The total DC miss latency (in processor cycles) across all IBS op samples that performed a load operation. The miss latency is the number of clock cycles from when the data cache miss was detected to when data was delivered to the core. Divide the total DC miss latency by the number of sampled load operations to obtain the average DC miss latency.

IBS Northbridge derived events

Event Select 0xF240 IBS NB local

Abbreviation: IBS NB local

The number of IBS op samples where a load operation was serviced from the local processor.

Northbridge IBS data is only valid for load operations that miss in both the L1 data cache and the L2 data cache. If a load operation crosses a cache line boundary, then the IBS data reflects the access to the lower cache line.

Event Select 0xF241 IBS NB remote

Abbreviation: IBS NB remote

The number of IBS op samples where a load operation was serviced from a remote processor.

Event Select 0xF242 IBS NB local L3 cache

Abbreviation: IBS NB local L3

The number of IBS op samples where a load operation was serviced by the local L3 cache.

Event Select 0xF243 IBS NB local core L1 or L2 cache

Abbreviation: IBS NB local cache

The number of IBS op samples where a load operation was serviced by a cache (L1 data cache or L2 cache) belonging to a local core which is a sibling of the core making the memory request.

Event Select 0xF244 IBS NB remote L1, L2 or L3 cache

Abbreviation: IBS NB remote cache

The number of IBS op samples where a load operation was serviced by a remote L1 data cache, L2 cache or L3 cache after traversing one or more coherent HyperTransport™ links.

Event Select 0xF245 IBS NB local DRAM

Abbreviation: IBS NB local DRAM

The number of IBS op samples where a load operation was serviced by local system memory (local DRAM via the memory controller).

Event Select 0xF246 IBS NB remote DRAM

Abbreviation: IBS NB remote DRAM

The number of IBS op samples where a load operation was serviced by remote system memory (after traversing one or more coherent HyperTransport links and through a remote memory controller).

Event Select 0xF247 IBS NB local APIC/MMIO/Config/PCI

Abbreviation: IBS NB local other

The number of IBS op samples where a load operation was serviced from local MMIO, configuration or PCI space, or from the local APIC.

Event Select 0xF248 IBS NB MMIO/Config/PCI

Abbreviation: IBS NB remote other

The number of IBS op samples where a load operation was serviced from remote MMIO, configuration or PCI space.

Event Select 0xF249 IBS NB cache Modified state

Abbreviation: IBS NB cache M

The number of IBS op samples where a load operation was serviced from local or remote cache, and the cache hit state was the Modified (M) state.

Event Select 0xF24A IBS NB cache Owned state

Abbreviation: IBS NB cache O

The number of IBS op samples where a load operation was serviced from local or remote cache, and the cache hit state was the Owned (O) state.

Event Select 0xF24B IBS NB local cache latency

Abbreviation: IBS NB local lat

The total data cache miss latency (in processor cycles) for load operations that were serviced by the local processor.

Event Select 0xF24C IBS NB remote cache latency

Abbreviation: IBS NB remote lat

The total data cache miss latency (in processor cycles) for load operations that were serviced by a remote processor.